基于FPGA的24×24位低功耗乘法器的设计  

Design of 24×24bit Low-power Multiplier Based on FPGA

作　　者：邢金朋[1] 李哲英[2] 

机构地区：[1]北京交通大学电子信息工程学院,北京100044 [2]北京联合大学微电子研究所,北京100101

出　　处：《现代电子技术》2010年第22期15-18,共4页Modern Electronics Technique

摘　　要：通过对现有编码算法的改进,提出一种新的编码算法,它降低功耗的方法是通过减少部分积的数量来实现的。因为乘法器的运算主要是部分积的相加,因此,减少部分积的数量可以降低乘法器中加法器的数量,从而实现功耗的减低。在部分积的累加过程中,又对用到的传统全加器和半加器进行了必要的改进,避免了CMOS输入信号不必要的翻转,从而降低了乘法器的动态功耗。通过在Altera公司的FPGA芯片EP2C70F896C中进行功耗测试,给出了测试结果,并与现有的两种编码算法进行了比较,功耗分别降低3.5%和8.4%。A new coding algorithm is introduced through improving the existed coding algorithms. The algorithm can decrease the power dissipation of multiplier with the method of reducing the number of partial production. The main operation of multiplier is the sum of partial productions, so this method can decrease the number of adder in multiplier and decrease the power dissipation of multiplier. During the sum of partial productions, it improves the basic structure of the traditional full- adder and half-adder, and reduces the activity rate of the input signal of CMOS, so decreases the dynamic power dissipation. Through comparison with multipliers which are designed with existed coding algorithms, the power dissipation of the improved coding algorithm is decreased by 3.5 % and 8.4 %.

关 键 词：乘法器 动态功耗 FPGA ASIC 

分 类 号：TN492-34[电子电信—微电子学与固体电子学]