Noise analysis and characterization of a full differential CMOS interface circuit for capacitive closed-loop micro-accelerometer  

作　　者：刘晓为 李海涛 尹亮 陈伟平 索春光 周治平 

机构地区：[1]Dept.of Microelectronics,Harbin Institute of Technology [2]Key Laboratory of Micro-Systems and Micro-Structures Manufacturing,Ministry of Education

出　　处：《Journal of Harbin Institute of Technology(New Series)》2010年第5期684-689,共6页哈尔滨工业大学学报（英文版）

基　　金：Sponsored by the National High Technology Research and Development Program of China(863Program)(Grant No.2008AA042201)

摘　　要：To achieve a high precision capacitive closed-loop micro-accelerometer,a full differential CMOS based on switched-capacitor circuit was presented in this paper as the sensor interface circuit.This circuit consists of a balance-bridge module,a charge sensitive amplifier,a correlated-double-sampling module,and a logic timing control module.A special two-path feedback circuit configuration was given to improve the system linearity.The quantitative analysis of error voltage and noise shows that there is tradeoff around circuit's noise,speed and accuracy.A detailed design method was given for this tradeoff.The noise performance optimized circuit has a noise root spectral density of 1.0 μV/Hz,equivalent to rms noise root spectral density of 1.63 μg/Hz.Therefore,the sensor's Brown noise becomes the main noise source in this design.This circuit is designed with 0.5 μm n-well CMOS process.Under a ±5 V supply,the Hspice simulation shows that the system sensitivity achieves 0.616 V/g,the system offset is as low as 1.456 mV,the non-linearity is below 0.03%,and the system linear range achieves ±5 g.To achieve a high precision capacitive closed-loop micro-accelerometer,a full differential CMOS based on switched-capacitor circuit was presented in this paper as the sensor interface circuit.This circuit consists of a balance-bridge module,a charge sensitive amplifier,a correlated-double-sampling module,and a logic timing control module.A special two-path feedback circuit configuration was given to improve the system linearity.The quantitative analysis of error voltage and noise shows that there is tradeoff around circuit＇s noise,speed and accuracy.A detailed design method was given for this tradeoff.The noise performance optimized circuit has a noise root spectral density of 1.0 μV/Hz,equivalent to rms noise root spectral density of 1.63 μg/Hz.Therefore,the sensor＇s Brown noise becomes the main noise source in this design.This circuit is designed with 0.5 μm n-well CMOS process.Under a ±5 V supply,the Hspice simulation shows that the system sensitivity achieves 0.616 V/g,the system offset is as low as 1.456 mV,the non-linearity is below 0.03%,and the system linear range achieves ±5 g. 更多还原

关 键 词：low noise full differential SWITCHED-CAPACITOR CLOSED-LOOP capacitive micro-accelerometer 

分 类 号：TN432[电子电信—微电子学与固体电子学]