基于Xilinx FPGA的时钟管理设计与实现  

Design and implementation of clock management based on Xilinx FPGA

作　　者：封彦彪[1] 刘兴春[1] 

机构地区：[1]北京航空航天大学电子信息工程学院,北京100083

出　　处：《电子测量技术》2010年第10期52-55,共4页Electronic Measurement Technology

摘　　要：介绍了时钟管理的各种实用方法。简要介绍了Xilinx FPGA的数字时钟管理模块(DCM)的组成和其在时钟倍频分频中的应用。重点分析了整数分频器和小数分频器的设计思想,对不同的分频方案进行了比较。在ISE9.1i集成开发环境中,用Verilog HDL语言编程,对设计的电路进行了功能仿真,给出了仿真波形。给出的多种分频方法具有非常好的可移植性,只需修改参数就可应用于FPGA的实际开发中。Practical methods for clock management are presented.The composition of Xilinx FPGA＇s digital clock management module and its application in clock frequency multiplication and division are described.The design ideas of integer and decimal frequency divider are analyzed,and different solutions are compared.In the integrated development environment of ISE 9.1i,Verilog language is used to realize the design goals.Also the function simulation of the design circuits is performed.The methods of frequency division design have excellent transportability,which can be easily used in the practical development of FPGA by altering the right parameter.

关 键 词：倍频 分频 FPGA 

分 类 号：TN791[电子电信—电路与系统]