基于IEEE1149.1标准的边界扫描控制器的设计  

Design of Boundary-scan Controller Based on IEEE1149.1 Standard

作　　者：高艳辉[1] 赵蕙[1] 肖铁军[1] 

机构地区：[1]江苏大学计算机科学与通信工程学院,江苏镇江212013

出　　处：《计算机测量与控制》2010年第11期2550-2552,共3页Computer Measurement &Control

摘　　要：为克服传统基于PC机的边界扫描测试系统所具有的独立性差、测试速度慢等缺点,从IEEE1149.1标准及边界扫描测试的功能需求入手,将边界扫描测试技术与SOPC技术相结合,提出了一种灵活、高效的嵌入式系统解决方案;该方案从IEEE标准及边界扫描测试的功能需求入手,设计了边界扫描测试系统的核心——边界扫描控制器,论文对该控制器的设计是采用自顶向下的模块化设计思想,VHDL语言描述实现;并将该控制器嵌入在具有Nios软核CPU的FPGA上,提高了系统设计的灵活性及边界扫描测试的速度;仿真结果表明该设计方案是正确可行的。In order to overcome the shorcomings of traditional PC-based system with poor independence,slow test speed and other shortcomings,this article combined the boundary-scan test technology and SOPC technology,then proposed a flexible and efficient embedded system solutions from the IEEE1149.1 standard and functional requirements of the boundary-scan testing.The program started to design the core of boundary-scan test system—boundary-scan controller from the IEEE standards and functional requirements of boundary-scan test.The controller design of this paper used top-down modular design,described and implemented with VHDL language.The controller was embedded with a Nios soft-core CPU in the FPGA,then improved the flexibility and speed of the boundary-scan test system.The simulation results show that the design is correct and feasible.

关 键 词：IEEE1149.1标准 边界扫描控制器 SOPC NIOSII处理器 

分 类 号：TN407[电子电信—微电子学与固体电子学]