一种面积与功耗优化的卷积器设计  

Design of Convolver with Area and Power Optimization

作　　者：陈琛[1] 陈赟[1] 曾晓洋[1] 

机构地区：[1]复旦大学微电子系集成电路与系统国家重点实验室,上海201203

出　　处：《计算机工程》2010年第22期236-238,共3页Computer Engineering

基　　金：上海市科委基金资助项目"高性能;低功耗抑制长回波干扰信道估计算法研究及其VLSI实现"(08700741100)

摘　　要：提出一种基于随机存取存储器(RAM)的卷积器结构。将2组阶数不同的卷积器进行VLSI实现,每组包含1个基于RAM结构的卷积器和1个基本型FIR结构的卷积器。DC及PrimePower分析结果表明,当阶数为63时,基于RAM结构的卷积器面积和功耗相比基本型FIR结构的卷积器分别减少10.1%和8.4%;当阶数为255时,该优化百分比分别为14.9%和15.2%,并且卷积器阶数越高,优化效果越明显。63阶卷积器成功流片后,芯片实测结果显示,与经典结构相比,基于RAM的卷积器功耗减少了7.9%。This paper proposes a novel architecture of convolver which is based on RAM. It is power and area efficient compared to the conventional FIR architecture which is based on registers. The reduction percentage of power and area increases with the order of the convolver. It implements two pairs of convolver with different orders. Each contains a RAM based one and a FIR one for comparison. Simulation results by DC and Prime Power show that for the first pair with order 63, area and power reduction percentages are 10.1% and 8.4% by employing RAM based architecture, while for the second pair the above reduction percentages are 14.9% and 15.2%. The chip test result when the first pair tape out successfully shows that the power reduction percentage is 7.9%.

关 键 词：卷积器 随机存取存储器 功耗 面积 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]