S/U双波段小数分频锁相环型频率合成器设计  

Design of S/U Dual-Band Fractional-N PLL Frequency Synthesizers

作　　者：刘永刚[1] 郭桂良[1] 杜占坤[1] 阎跃鹏[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《半导体技术》2010年第11期1106-1110,共5页Semiconductor Technology

基　　金：国家高技术研究发展(863)计划(2007AA01Z2a8)

摘　　要：提出了一种覆盖S/U双波段的小数分频锁相环型频率合成器。该频率合成器采用一种新型多模分频器,与传统的小数分频频率合成器相比具有稳定速度快、工作频率高和频率分辨率高的优点。该锁相环采用了带有开关电容阵列（SCA）的LC-VCO实现了宽频范围,使用3阶MASHΔ-Σ调制技术进行噪声整形,降低了带内噪声。设计基于TSMC 0.25μm 2.5 V 1P5M CMOS工艺实现。测试结果表明,频率合成器频率范围达到2.450~3.250 GHz;波段内偏离中心频率10 kHz处的相位噪声低于-92.5 dBc/Hz,1 MHz处的相位噪声达到-120 dBc/Hz;最小频率分辨率为13 Hz;在2.5 V工作电压下,功耗为36 mW。An S/U dual-band fractional-N PLL frequency synthesizer（FS） was proposed.A novel multi-modulus divider was used in the synthesizer.Compared with the traditional fractional-N PLL frequency synthesizer,the design showes good performances of the fast settling time,high working frequency and high resolution.An LC tank voltage-controlled oscillator（VCO）with switched-capacitors array（SCA） was used to achieve a wide-band frequency range.The fractional-N PLL frequency synthesizer with 3-order sigma-delta modulator was realized in TSMC 0.25 μm 2.5 V CMOS process.The test results show that the working frequency is 2.450-3.250 GHz,the measured phase noise is lower than-92.5 dBc/Hz at 10 kHz offset and-120 dBc/Hz at 1 MHz offset,with the ultra-small step size less than 13 Hz.The frequency synthesizer consumes 36 mW from a single 2.5 V supply voltage.

关 键 词：频率合成器 小数分频锁相环 相位噪声 Δ-Σ调制器 压控振荡器 

分 类 号：TN742[电子电信—电路与系统]