64位超前进位对数加法器的设计与优化  

Design and Optimization of 64-Bit Look-Ahead Logarithmic Adders

作　　者：王仁平[1] 何明华[1] 陈传东[1] 戴惠明[1] 黄扬国[1] 

机构地区：[1]福州大学物理与信息工程学院,福州350108

出　　处：《半导体技术》2010年第11期1116-1121,共6页Semiconductor Technology

基　　金：福建省区域科技重大项目(2009HZ010002);福建省自然科学基金(重点)(2007J0003);福建省教育厅(JA09001)

摘　　要：设计一个应用于高性能微处理器的快速64位超前进位对数加法器。通过分析超前进位对数加法器原理,提出了改进四进制Kogge-Stone树算法的64位超前进位对数加法器结构,并结合使用多米诺动态逻辑、时钟延迟多米诺逻辑和传输门逻辑等技术来设计和优化电路。该加法器采用SMIC 0.18μm CMOS工艺实现,在最坏情况下完成一次加法运算时间为486.1 ps,与相同工艺和相同电路结构采用静态CMOS实现相比,大大减少了加法器各级门的延迟时间,取得良好的电路性能。A fast 64-bit look-ahead logarithmic adder applying to high-performance microprocessors was designed. By analyzing the look-ahead adder, the 64-bit look-ahead logarithmic adder structure was proposed, which based on the improved radix-4 Kogge-Stone tree algorithm, and combined the domino dynamic logic, clock-delay domino logic and transmission gate to design and optimize the circuit. Using SMIC 0.18 μm CMOS process, in the worst case, the computation time is 486.1 ps, which greatly reduces all levels of the gate delay time and makes a good performance compared with that of the circuit based on the static CMOS with the same process and circuit structure.

关 键 词：多米诺动态逻辑 时钟延时多米诺 对数加法器 点操作 Kogge-Stone树 

分 类 号：TN432[电子电信—微电子学与固体电子学]