流水线ADC级间增益误差的数字域补偿方法  

Digital calibration of interstage gain errors in pipelined ADC

作　　者：彭隽[1,2] 谭萍[1,2] 马洪[1,2] 胡啸[1,2] 

机构地区：[1]华中科技大学电子与信息工程系,湖北武汉430074 [2]华中科技大学武汉光电国家实验室,湖北武汉430074

出　　处：《华中科技大学学报（自然科学版）》2010年第11期29-32,共4页Journal of Huazhong University of Science and Technology(Natural Science Edition)

基　　金：国家自然科学基金资助项目(10975056)

摘　　要：提出了一种针对流水线模数转换器(ADC)级间残差放大器的线性增益偏差与增益压缩误差的后台补偿方法.利用随机信号的二阶统计互相关特性,通过在第一级数模转换器输入端的低两位上分次注入数字伪随机序列,测量放大器的实际增益值与其表征幂级数模型的三阶非线性项系数,并使用此估计值同时完成对这两种误差的后台补偿.为了验证设计,对14位三级流水线ADC进行了系统模拟,当前两级量化精度均为5位,且两级残差放大器的增益偏差与输出峰值点的相对增益压缩率分别为-2%和5%时,经过补偿后SFDR(无杂散失真动态范围)和SNDR(信噪失真比)指标分别从70.93dB和54.83dB提高到97.60dB和74.30dB.A digital background calibration was proposed to post-correct linear gain deviations and gain compression errors from interstage residue amplifiers in pipelined analog to digital converter（ADC）. By means of adding digital pseudo-random sequence at two different bit position of the first-stage DAC （digital to analog converter）input,second-order cross-correlation information for the measurement of both actual gain of the residue amplifier and third-order nonlinear coefficient of the power series modeling the amplifier nonlinearity were used in the method,gain errors could then be background-calibrated using the estimated values.Simulations are performed for a 14bit pipelined ADC with three stages.Assuming the first two 5bit stages both have the linear gain error of-2%and third-order nonlinearity corresponding to a gain compression of 5%at full scale,results show that with this calibration scheme,spurs free dynamic range（SFDR）and signal to noise distortion ratio（SNDR）would be improved from 70.93dB,54.83dB to 97.6dB,74.3dB respectively.

关 键 词：流水线ADC 级间残差放大器 增益偏差 增益压缩误差 后台补偿 

分 类 号：TN792[电子电信—电路与系统]