基于FPGA的并行FIR数字滤波器硬件实现及优化  

HARDWARE IMPLEMENTATION'S OPTIMIZATION OF FPGA-BASED PARALLEL FIR DIGITAL FILTERS

作　　者：付正[1] 郑维智[1] 江远志[1] 

机构地区：[1]北京工商大学机械工程学院,北京100048

出　　处：《北京工商大学学报（自然科学版）》2010年第5期69-74,共6页Journal of Beijing Technology and Business University:Natural Science Edition

基　　金：北京市教育委员会科技计划项目(KM200810011007)

摘　　要：阐述了基于有限脉冲响应数字滤波器FIR的可编程逻辑器硬件实现的优化和改进方案.介绍了FIR滤波器原理及传统线性FIR滤波器的实现结构,提出了并行FIR滤波器的结构改进思路,详细地说明了各模块具体功能的实现及采用技术,最后给出了并行FIR的拓展应用方案.The hardware implementation and optimization and improvement proposal for FPGA-based Parallel FIR digital filters were detailed in this paper.The principle of FIR filter and the implementation structure of traditional linear FIR filter were introduced,and thoughts of optimization and improvement for Parallel FIR digital filters were proposed.Each module＇s specific functions and technology were set out,and parallel FIR digital filters＇ expansion applications were then put forward.

关 键 词：现场可编程逻辑器件 硬件描述语言 Max-plusⅡ 有限脉冲响应数字滤波器 

分 类 号：TN911.4[电子电信—通信与信息系统]