高性能中频采样系统的设计与实现  

Design and implementation of high performance IF sampling system

作　　者：黄丽莲[1] 李子绪[1] 

机构地区：[1]哈尔滨工程大学信息与通信工程学院,黑龙江哈尔滨150001

出　　处：《电子设计工程》2010年第12期1-4,共4页Electronic Design Engineering

基　　金：国家自然科学基金资助(60772025);中央高校基本科研业务费专项资金资助

摘　　要：为提高中频采样系统性能,降低板级噪声,加大采样频率的灵活性,设计并实现一种高性能中频采样系统。该系统利用AD9518-4实现可配置的采样时钟,根据不同的采样要求,AD9518-4可提供多路不同频率的输出。系统还采用AD8352型运算放大器作为A/D转换器前端驱动电路,将单端中频输入信号转换为差分信号,并进行相应放大,滤波等工作,配合AD9445型A/D转换器,获得14位低电压差分输出信号。实验结果表明,该系统在40MHz中频信号输入的情况下,信噪比达到77.4dBFS,并可实现采样时钟的可编程配置。与传统方案相比,该采样系统信噪比、无杂散动态范围,有效比特位等性能指标都得到明显改善。With the aim of improving the performance of IF sampling system, reduce the board-level noise, increase the flexibility of the sampling system, this paper designs and implements a high performance IF sampling system. The system implements a configurable sampling clock with AD9518-4 device. AD9518-4 can provide muhichannel outputs with different frequency. The system uses AD8352 operational amplifier which can transform the single-ended signal into the differential signal, amplify and filter the signal as the driver of ADC front-end. The system can obtain 14bit low voltage differential signal with AD9445 analog digital converter. Experimental results show that, the signal to noise rate can reach 77.4dBFS when the input signal frequency is 40MHz and the system can achieve a configurablc sampling clock. The RSN, SFDR and ENOB of the sampling system are all obviously improved compared with the traditional scheme.

关 键 词：中频采样 模数转换器 时钟抖动 AD9445 AD9518 AD8352 

分 类 号：TN79[电子电信—电路与系统]