基于改进CORDIC算法实现高速直接数字频率合成器  

Implementation of a high-speed direct digital frequency synthesizer based on improved CORDIC algorithm

作　　者：万书芹[1] 陈宛峰[1] 黄嵩人[1] 季惠才[1] 于宗光[1,2] 

机构地区：[1]中国电子科技集团公司第58研究所,无锡214035 [2]江南大学信息工程学院,无锡214122

出　　处：《仪器仪表学报》2010年第11期2586-2591,共6页Chinese Journal of Scientific Instrument

基　　金：江苏省自然科学基金(BK2007026);"333高层次人才培养工程"专项(2007124);广东省部产学研合作引导项目(2009B090300416)资助

摘　　要：设计实现了一种高速直接数字频率合成器。利用混合CORDIC算法的思想,用混合角度集代替传统正切角度集,并讨论了在二进制格式下的中间值,采用改进的混合差分CORDIC算法实现了相位幅度的转换。在确保算法的迭代精度和收敛区间的前提下,避免了传统算法中旋转方向依赖于上一次迭代的现象,提高了数据的吞吐量;同时消除了常用冗余算法引进额外电路的情况。分析了采用CORDIC算法所带来的误差,综合考虑精度和电路复杂度,确定字长和迭代次数获得14位的输出有效位。经0.18μm6M2P CMOS工艺流片,在1GHz的工作频率下,输出信号在98.6MHz处,SFDR为68.39dB,整个芯片面积为4.19mm×3.17mm。A high-speed direct digital frequency synthesizer was designed. The idea of hybrid coordinate rotational digital computer （CORDIC） algorithm is adopted, which uses a mixed angle set to replace traditional ARC tangent angle set. The middle value of hybrid angle group with binary format is discussed; an improved hybrid differential CORDIC algorithm is introduced to implement the phase-to-amplitude converter. This method avoids the fact that the next iteration depends on the results of the previous iteration, improves the data throughput and eliminates the needed additional circuits that commonly used redundant algorithms require to add. After considering the computation accuracy and circuit complexity, the data path width and iteration number are determined; and 14-bit output effective bit number is obtained. The DDFS was fabricated in 0.18 μm N-well 6M2P CMOS process.The measured SFDR is 68.39 dB with at output frequency of 98.6 MHz under 1 GHz clock frequency. The chip area is 4.19 mm×3.17 mm.

关 键 词：直接数字频率合成器 CORDIC算法 差分CORDIC 混合角度集 

分 类 号：TN742.1[电子电信—电路与系统]