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机构地区:[1]Microelectronics School,Xidian University
出 处:《Chinese Physics B》2010年第12期530-536,共7页中国物理B(英文版)
基 金:Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60971066);the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260);the National Science & Technology Important Project of China (Grant No. 2009ZX01034-002-001-005)
摘 要:Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing arid adopting low-swing interconnect technology, this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously. The optimized model is verified based on 65-am and 90-nm complementary metal-oxide semiconductor (CMOS) interconnect parameters. The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process. The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing arid adopting low-swing interconnect technology, this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously. The optimized model is verified based on 65-am and 90-nm complementary metal-oxide semiconductor (CMOS) interconnect parameters. The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process. The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.
关 键 词:interconnect power repeater area low-swing circuit time delay BANDWIDTH
分 类 号:TN47[电子电信—微电子学与固体电子学]
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