用Design Compiler进行逻辑综合概述  

The Summary of Doing Logic Synthesis By Using Design Compiler

作　　者：杨光[1] 赵庆哲[1] 

机构地区：[1]中国电子科技集团公司第四十七研究所,沈阳110032

出　　处：《微处理机》2010年第5期32-34,共3页Microprocessors

摘　　要：逻辑综合是RTL到GDSII设计流程中非常关键的一步。理解逻辑综合的过程,掌握逻辑综合的策略,是进行逻辑综合的前提条件。给目标设计施加完整的综合约束,创建逻辑综合脚本,分析综合结果,是进行逻辑综合过程中必要的步骤。Logic synthesis is a very key step of RTL to GDSII design flow.It is a prerequisite for understanding the process of synthesis and mastering the strategies of synthesis during logic synthesis.It is an essential process of applying complete logic constraints on the target design,creating logic synthesis scripts and making an analysis of synthesis results during logic synthesis.

关 键 词：逻辑综合 综合约束 综合策略 

分 类 号：TN4[电子电信—微电子学与固体电子学]