9B/10B调制码设计与实现  

Design and implementation of 9B/10B modulation code

作　　者：周少飞[1] 马骋[1] 贾惠波[1] 

机构地区：[1]清华大学精密测试技术及仪器国家重点实验室,北京100084

出　　处：《微计算机信息》2010年第33期145-146,149,共3页Control & Automation

摘　　要：为了进一步提高高速数据传输系统的有效传输速率,本文提出一种9B/10B调制码设计方案。该方案具有90%的高编码效率,并且具有DC平衡、码字游程长度受限、编解码算法简单,易于硬件实现等特点。对9B/10B硬件编码器与解码器的相关性能进行测试,测试结果表明该方案编码效率高、占用逻辑资源少,适用于高速串行数据的传输。A implementing method of 9B/10B encoding and decoding is proposed to further increase the effective transmission rate in the high-speed data transmission system. The bit rate of 9B/10B modulation code is 90%. The proposed method has the advantages as DC-free, run-length-limited, low computation complexity and easily realized with hardware. Test the performance of 9B/10B encoder and decoder with FPGA, and the result shows that the proposed method is with high code rate and few logic resources consumption and has application in high-speed serial data transmission.

关 键 词：9B/10B码 码字映射 DC平衡 

分 类 号：TN91[电子电信—通信与信息系统]