新型低功耗单/双边沿触发器的比较分析  

Comparative Analysis of New Low-Power Single-and Double-Edge Flip-Flops

作　　者：蔡艳慧[1] 方赟[1] 钟传杰[1] 

机构地区：[1]江南大学信息工程学院,江苏无锡214122

出　　处：《微电子学》2010年第6期836-839,843,共5页Microelectronics

基　　金：科技部技术创新基金资助项目(07C26223201317)

摘　　要：在深入分析边沿触发器的功耗理论和时间特性的基础上,提出了新的设计方案。在SMIC 0.35μm CMOS标准工艺下,对该方案进行Spectre仿真,结果表明:新型结构比传统结构的延时下降48%左右,功耗下降26.22%。并且,在新设计方案中,双边沿触发器比单边沿触发器的延时下降36%,功耗下降19%。由此可见,新型边沿触发器,特别是新型双边沿触发器,不但能有效降低集成电路的功耗,而且对提高微系统的速度也有一定贡献。A novel edge flip-flop was designed based on study of power consumption theory and time characteristics of edge flip-flops.Results from Spectre simulation based on SMIC＇s 0.35 μm CMOS standard process showed that the delay and power consumption of the novel edge flip-flop was reduced by 48% and 26.22%,respectively,compared with the conventional structure.Furthermore,in the new design,the double-edge flip-flop had a delay and power consumption 36% and 19% lower,respectively,than the single-edge flip-flop.It can be concluded that the novel edge flip-flop,especially double-edge flip-flop,can not only reduce power consumption of IC＇s,but also speed up microsystems.

关 键 词：能量回收 时钟分配网络 单边沿触发 双边沿触发 触发器 

分 类 号：TN432[电子电信—微电子学与固体电子学]