帧长可配置QPP交织器的FPGA设计  

Design of QPP Interleaver with Variable Frame Length Based on FPGA

作　　者：赵旦峰[1] 朱铁林[1] 刘渊[2] 

机构地区：[1]哈尔滨工程大学信息与通信工程学院,哈尔滨150001 [2]西北工业大学电子信息学院,西安710129

出　　处：《微电子学》2010年第6期840-843,共4页Microelectronics

基　　金：哈尔滨市科技创新专项(2009RFXXG029)

摘　　要：针对传统固定交织器灵活性和适应性差的特点,在LTE标准下,提出了一种基于FPGA的可变帧长QPP交织器的硬件实现方案。采用"自上而下"的设计思想和"自下而上"的实现流程相结合的方法,根据FPGA自身特点,将QPP交织算法巧妙地转化为硬件语言进行描述,对特定功能模块进行优化设计后调试统一。将设计的交织器应用于Turbo码编译码器中,下载配置到Xilinx公司的Virtex-2 Pro系列芯片,依据信道环境修改编码码长,使译码性能与时延达到最佳平衡,具有很好的移植性和通用性。In view of the poor flexibility and adaptability of interleaver with fixed frame length,scheme for FPGA implementation of QPP interleaver with variable frame size in LTE was proposed.In this scheme,＂top-down＂ design idea and ＂bottom-up＂ method were adopted.Utilizing characteristics of FPGA,the complicated QPP interleaving algorithm was transformed to hardware language,which could be easily carried out.Specific function modules were debugged after optimization design.The proposed interleaver was applied to codec for Turbo codes and configured into Virtex-2 Pro series of Xilinx.It could change code length along with channel environment.The design also achieved optimal balance between decoding performance and latency.It has very good portability and versatility.

关 键 词：TURBO码 QPP交织器 FPGA 可变帧长 

分 类 号：TN764[电子电信—电路与系统] TN47