基于CPLD的高精度全数字锁相环  

High accuracy ADPLL based on CPLD

作　　者：熊学海[1] 付志红[1] 李胜芳 林伟 

机构地区：[1]重庆大学输配电装备及系统安全与新技术国家重点实验室,重庆400030 [2]重庆电力科学试验研究院,重庆401123

出　　处：《电子技术应用》2010年第12期58-61,共4页Application of Electronic Technique

基　　金：国家自然科学基金(40874094);重庆大学"211工程"三期创新人才培养计划建设项目(S-09111)

摘　　要：针对由电力系统工频信号频率波动导致的不能同步采样从而影响电参量测量精度的问题,提出以74HC297为核心设计高精度的全数字锁相环(ADPLL)电路,实现精密跟踪锁定待测信号频率和相位,并在CPLD中实现。本文推导ADPLL在频率跳变时的锁定时间表达式,分析影响锁定速度和精度的相关因素。给出实验波形和数据,实验结果表明,该ADPLL的锁定精度至少达到0.000 2 Hz以上。The frequency of power system ofen waves and this affects the accuracy of measurement. Aiming at this problem, this paper designs all digital phase-locked loop （ADPLL） circuit based on 74HC297. The ADPLL which is achieved in CPLD can exactly track and lock the frequency and phase of the signal which is measured. This paper deduces the formula of ADPLL＇s lock time when the frequency of input signal has changed, and analyzes the factors which impact the lock time and accuracy. The wave and data of experiments are supplyed, and the results of experiments show that the ADPLL＇ s lock accuracy at least exceeds 0.000 2 Hz.

关 键 词：全数字锁相环(ADPLL) 锁定时间 锁定精度 频率跟踪 

分 类 号：TM935[电气工程—电力电子与电力传动]