JTIDS传输符号产生模块的FPGA设计  

Design of JTIDS Transmission Code Generator Based on FPGA

作　　者：牛强军[1] 莫新康[2] 赵文俊[1] 宋家友[2] 

机构地区：[1]空军第一航空学院航空电子工程系,河南信阳464000 [2]郑州大学信息工程学院,郑州450001

出　　处：《电讯技术》2010年第12期43-47,共5页Telecommunication Engineering

基　　金：空军科研计划资助项目(KJ2010218)~~

摘　　要：根据公开的关于Link16数据链的信息标准并结合对战术数据链的具体要求,设计了一种JTIDS传输符号产生模块,该模块包含RS编码、交织、CCSK软扩频、CCSK码字加密等若干子模块。首先介绍了Link16数据链传输符号的产生原理,对其各个子处理模块进行了设计并提出了硬件实现方案,然后在Quartus Ⅱ环境下选择Cyclone Ⅱ系列的EP2C8Q208C8 FPGA芯片进行了JTIDS传输符号产生模块的系统级综合与仿真,并在该芯片的开发板上进行了验证,硬件成品可用于JTIDS终端功能测试与评估等多种场合。According to the public Link16 information criteria, a JTIDS transmission code generator is designed combining with the requirements for tactical data link（TDL）, in which submodules such as RS encoding, interleaving, CCSK, and CCSK codes encryprion are contained. Based on the principle of Link16 transmission code generator, the submodules are designed and the scheme of hardware implementation is given. Systemic synthesis and simulation for the transmission code generator are accomplished on the Quartus II software platform with Cy- clone II FPGA chip EP2C8Q208C8, and is verified on the development board with Cyclone II FPGA chip. The hardware product can be used to test and evaluate the function of the data link and so on.

关 键 词：联合战术信息分发系统 战术数据链 RS编码 循环码移位键控 伪随机序列 

分 类 号：TN919.3[电子电信—通信与信息系统] TN919.4[电子电信—信息与通信工程]