基于DSP Builder和FPGA的IIR滤波器设计  

IIR Filters Design Based on DSP Builder and FPGA

作　　者：杨世华[1] 王秀敏[1] 陈豪威[1] 

机构地区：[1]中国计量学院信息工程学院,浙江杭州310018

出　　处：《通信技术》2010年第12期184-186,共3页Communications Technology

基　　金：国家质检总局科技项目(编号:2009QK027);浙江省科技计划优先主题重点工业项目(编号:2010C11024)

摘　　要：针对传统的基于现场可编程门阵列(FPGA)的数字滤波器设计所需周期长,提出了基于dsp builder和FPGA的滤波器设计,完全实现自顶向下的设计流程。在此基础上设计实现四节级联IIR,并结合MATLAB强大计算功能,提出了利用MATLAB和Quartus II联合仿真算法;使输出复杂的数据变为波形,易于观察仿真结果,增强了Quartus的仿真功能。结果表明设计的IIR滤波器完全达到设计要求。To overcome the long cycle in digital filter design based on FPGA,a top-down design method based on DSP builder and FPGA is proposed,with which a 4-order cascade IIR filter is designed.With the strong calculation capacity of Matlab,a simulation method in combination of MATLAB with Quartus II is proposed.By converting the complex data to waveform,the simulation result becomes easier for observation,the simulation function of Quartus II is also enhanced.The results show that the IIR digital filter can fully meet the design requirement.

关 键 词：语言信号处理 级联 数字滤波器 

分 类 号：TP391.9[自动化与计算机技术—计算机应用技术]