基于VHDL的生产线定时计数系统设计  

Design of Timing and Count System of Production Line based on VHDL

作　　者：张俊梅[1] 李锦清[1] 刘芷宁[1] 石磊[1] 

机构地区：[1]北京林业大学工学院,北京100083

出　　处：《微计算机信息》2010年第35期12-14,共3页Control & Automation

基　　金：北京林业大学大学生科研训练计划项目"基于CPLD的微型计算机新型接口设计"(NO:91008)研究成果之一

摘　　要：定时计数系统在自动化生产线中有着广泛的用途。本文采用VHDL硬件描述语言,运用自顶向下的设计思想设计了生产线中定时计数系统。文中给出了系统硬件连接图、总体逻辑结构图并进行了逻辑仿真。结果表明,该定时计数系统设计功能正确,结构简单、控制精确。The timing and count system is an important part of automatic production line.In this paper,the design of timing and count system of production line based on VHDL（Very high speed IC Hardware Description Language） by the top-down method was put forward.The hardware diagram,logic design of the system,and logic simulation were described in detail.The results show that the whole designed system based on VHDL has the advantages of accurate functions,simple structure,and good flexibility.

关 键 词：定时计数 VHDL硬件描述语言 逻辑仿真 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]