A statistical RCL interconnect delay model taking account of process variations  

作　　者：朱樟明 万达经 杨银堂 恩云飞 

机构地区：[1]Microelectronics School,Xidian University

出　　处：《Chinese Physics B》2011年第1期659-666,共8页中国物理B（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(Grant Nos.60725415 and 60971066);the National Science&Technology Important Project of China(Grant No.2009ZX01034-002-001-005);The National Key Laboratory Foundation(Grant No.ZHD200904)

摘　　要：As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. The proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. The proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.

关 键 词：process variation interconnect line statistical delay successive linear approximation 

分 类 号：TN432[电子电信—微电子学与固体电子学]