基于FPGA的CMI编码系统设计  

Design of CMI encoded system based on FPGA

作　　者：王海滨[1] 

机构地区：[1]海军飞行学院教研部航空电子教研室,辽宁葫芦岛125001

出　　处：《电子设计工程》2011年第1期62-65,共4页Electronic Design Engineering

摘　　要：提出了一种基于FPGA并利用Verilog HDL实现的CMI编码设计方法。研究了CMI码型的编码特点,提出了利用Altera公司CycloneⅡ系列EP2C5Q型号FPGA完成CMI编码功能的方案。在系统程序设计中,首先产生m序列,然后程序再对m序列进行CMI码型变换。在CMI码型变换过程中,采用专用寄存器对1码的状态进行了存储,同时利用m序列的二倍频为CMI编码进程提供时钟激励,最后输出CMI码型。实验结果表明,采用FPGA完成CMI编码的设计,编码结果完全正确,能够达到预期要求。利用这种方法实现CMI编码功能,具有效率高、可扩展性强、升级方便等特点,方便嵌入到大规模设计中,具有广泛的应用前景。In order to implement CMI encoded system, a method based on FPGA and programmed with Verilog HDL is presented. Based on the research of CMI encoded characteristic, EP2C5Q of Ahera corporation Cyclone Ⅱ FPGA is used to finish CMI encoded function. In the design of system program, m series were generated at first, then the m series were transformed into CMI code. In the process of CMI encoding, a special register is used to save the state of code 1, at the same time, the clock of CMI encoding process is provided by two times m series＇ clock, then the CMI code was output. The experiment results indicate that using the FPGA to implement CMI encoded, the encoded result is completely correct, it can achieve the prospective requirements. This method has the excellent characteristic of high efficiency, extended quality and convenient upgrade, the design is easily embedded into a large system and has wide prospect in practical application.

关 键 词：FPGA VERILOGHDL 传号反转码(CMI) 编码 M序列 

分 类 号：TP762[自动化与计算机技术—检测技术与自动化装置]