A 12-bit 40-MS/s SHA-less pipelined ADC using a front-end RC matching technique  

作　　者：范明俊 任俊彦 舒光华 过瑶 李宁 叶凡 许俊 

机构地区：[1]State Key Laboratory of ASIC & Systems Fudan University [2]Micro-Nanoelectronics Science and Technology Innovation Platform,Fudan University [3]The MediaTek Inc.

出　　处：《Journal of Semiconductors》2011年第1期85-89,共5页半导体学报（英文版）

基　　金：Project supported by the National High Technology Research and Development Program of China(No.2008AA010702)

摘　　要：A12-Bit 40-MS/s pipelined analog-to-digital converter （ADC） incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity in SHA-less architecture without tedious verification in back-end layout simulation. Employing SHA-less, opampsharing and low-power opamps for low dissipation and low cost, designed in 0.13μm CMOS technology, the prototype digitizes a 10.2-MHz input with 78.2-dB of spurious free dynamic range, 60.5-dB of signal-to-noise- and-distortion ratio, and -75.5-dB of total harmonic distortion （the first 5 harmonics included） while consuming 15.6-mW from a 1.2-V supply.A12-Bit 40-MS/s pipelined analog-to-digital converter （ADC） incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity in SHA-less architecture without tedious verification in back-end layout simulation. Employing SHA-less, opampsharing and low-power opamps for low dissipation and low cost, designed in 0.13μm CMOS technology, the prototype digitizes a 10.2-MHz input with 78.2-dB of spurious free dynamic range, 60.5-dB of signal-to-noise- and-distortion ratio, and -75.5-dB of total harmonic distortion （the first 5 harmonics included） while consuming 15.6-mW from a 1.2-V supply.

关 键 词：analog-to-digital converter opamp-sharing RC matching SHA-less LOW-POWER 

分 类 号：TN792[电子电信—电路与系统]