基于FPGA实现高速串行链路数据恢复的方法  

Data Recovery Method of High-Speed Serial Link Based on FPGA

作　　者：曲伟[1] 孙志安[1] 

机构地区：[1]中国船舶重工集团公司江苏自动化研究所,江苏连云港222006

出　　处：《计算机测量与控制》2011年第1期219-221,共3页Computer Measurement &Control

摘　　要：为解决高速串行链路数据时钟异步时数据恢复问题,提出了基于FPGA的高速串行链路数据恢复方案,设计了本地时钟与锁相环输出时钟组成的混合时钟域,阐述了在不同相位高速串行数据采样原理与采样过程,分析了采样位置判决原理与数据有效判别方法,实现了高速串行链路数据的恢复;通过逻辑仿真与试验验证,在时钟速率与数据速率不同的情况下,该方法能够有效恢复串行数据,数据速率可达400Mb/s,在数据通讯领域有广泛应用前景。In order to recover data from the high-speed serial link when the data and clock arc not synchronous, the FPGA-based data recovery solution is proposed. This paper designs the clock domains composed of the local clock and the PLL output clock, describes the high-speed serial data sampling theory and sampling process in the different phase domains, analyzes the sampling position judgment and data effectiveness identification method, realizes the data recovery from high-speed serial links. By the simulation and practical validation, even though the clock rate is different from the data rate, this method can restore data from the serial link effectively, data rates can up to 400Mb / s, the method has a wide application prospects in data communications.

关 键 词：高速串行链路 数据恢复 FPGA 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]