基于DDR IP核视频图像缓存的设计与实现  

Design and Implement of Video Image Buffer Based on DDR IP Core

作　　者：熊璟[1] 唐广[1] 唐湘成[2] 黄自力[2] 

机构地区：[1]电子科技大学电子工程学院,四川成都611731 [2]西南技术物理研究所,四川成都610041

出　　处：《电视技术》2011年第2期48-50,共3页Video Engineering

摘　　要：在现代图像采集显示系统中,常常需要用到大容量、高速度的存储器,DDR为当前存储器应用的主流。采用了64 bit数据位宽的DDR IP核利用DDR的双倍数据传输速度的优点并结合了双口RAM的高速缓存特点,基于Altera公司的CycloneⅢ系列FPGA开发板在两种平台下实现了数据传输和图像缓存,并使用逻辑分析仪Signal TapⅡ对设计进行调试和分析。Nowadays, memory which have big capability and high-speed in image collecting system is needed. DDR can meet the requirements, so it is the artery of memory at present. In this paper, DDR IP core with 64 bit data width is used, it adopted double data rate of DDR and the high-speed buffer specialty of RAM-2port to achieve data transfer and image buffer on two situations which are based on the FPGA exploit board of Cyclone Ⅲ series of Quartus Ⅱ of Altera company, the design of the system on Signal Tap Ⅱ which is a logic analysis tool is debugged and analyzed.

关 键 词：DDR 双口随机访问存储器 图像缓存 CYCLONE Ⅲ 

分 类 号：TN941.1[电子电信—信号与信息处理]