高速ADC时钟抖动及其影响的研究  

Research of clock jitter and its effect on high-speed data conversion

作　　者：胡智宏[1] 廖旎焕[2] 

机构地区：[1]郑州轻工业学院电气工程学院,河南郑州450002 [2]华北水利水电学院电力学院,河南郑州450010

出　　处：《微型机与应用》2011年第2期85-88,共4页Microcomputer & Its Applications

摘　　要：从ADC的输入信号及时钟源的自身参数着手,主要分析了输入信号幅值、频率、采样频率对时钟抖动及ADC信噪比的影响,根据ADC手册数据提供的信息给出了时钟抖动的计算方法,并对计算结果和实际测量结果进行分析比较,进一步提出了减少时钟抖动方法。The effect on clock jitter and the SNR of the ADC caused by the input amplitude,input frequency and sampling frequency is studied in this paper. The mathematical estimated method of clock jitter is given based on the data sheet of ADC,and the results of the measurements are analyzed. The real measured result and the estimated result were compared. Some methods to minimize the clock jitter are put forward.

关 键 词：时钟抖动 SNR 频率 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术]