基于FPGA实现的减小DRAM延迟的Cache的设计  

作　　者：王玥[1] 付强[1] 

机构地区：[1]广西工学院鹿山学院

出　　处：《科学时代》2011年第1期76-78,共3页SCIENCE TIMES

摘　　要：本文的Cache是本人为网络安全加速卡NSA所设计的，它主要用来消除DRAM（Dynamic Random Access Memory）的延迟时间，加快系统运行速度．由于此项目是用FPGA实现的，所以本文采用FPGA内部的CAM（Content Addressable Memory）和RAM（Random Access Memory）来实现Cache以达到减小DRAM延迟的目的。与传统Cache相比它简单容易实现、节省FPGA内部资源而且性能又不比传统Cache差。它加快了数据的返回速度，提升了系统性能。The Cache in this article is designed for the Network Security Accelerator card named NSA, which is mainly used to eliminate delay time of the DRAM （Dynamic Random Access Memory） and accelerate the system speed.This project is achieved with FPGA, so this paper uses CAM （Content Addressable Memory） and RAM （Random Access Memory） in FPGA to realize the Cache in order to implement the purpose of reducing the DRAM latency. Compared with the traditional Cache, it is simple and easy to comply, saving resources within the FPGA ,and the performance is not worse than traditional Cache. It not only accelerates the return speed of data. but also improves system performance.

关 键 词：CAM RAM CACHE FPGA 

分 类 号：TP312[自动化与计算机技术—计算机软件与理论]