基于平均幅度和加权过零率的VAD算法及其FPGA实现  

Voice Activity Detection Algorithm and Its Implementation Based on Magnitude and Weighted Zero Crossing Rate

作　　者：周明忠[1] 吉立新[1] 

机构地区：[1]信息工程大学国家数字交换系统工程技术研究中心,河南郑州450002

出　　处：《信息工程大学学报》2010年第6期713-718,共6页Journal of Information Engineering University

基　　金：国家863计划资助项目(2008AA011001)

摘　　要：介绍了一种平均幅度和加权过零率的VAD算法,并对该算法进行了硬件实现。对其中主要的模块,在硬件实现方法上进行了优化,取得了较好效果,使其在保证实时性要求的同时节省了资源,为进一步向低成本器件上移植或系统中作为IP模块应用提供了可能性。This paper introduces a VAD algorithm with average of the magnitude and weighted zero crossing rate,and the algorithm has been implemented by hardware.The major modules have achieved good effects which have been optimized in the hardware implementation,thus ensuring real-time requirements and saving resources.The algorithm offers the possibility for further migration to low-cost device or system IP module applications.

关 键 词：语音激活检测 短时能量 短时过零率 现场可编程门阵列 

分 类 号：TN912.3[电子电信—通信与信息系统]