前置相序分解型dq锁相环性能分析与仿真研究  

Performance Analysis and Simulation of the dq-PLL with Anti-SSM

作　　者：周国梁[1] 刘宣宣[1] 石新春[2] 

机构地区：[1]中南电力设计院,武汉430071 [2]华北电力大学,河北保定071003

出　　处：《南方电网技术》2010年第6期65-69,共5页Southern Power System Technology

基　　金：教育部博士点基金项目(20070079007)~~

摘　　要：针对传统dq锁相环以抑制负序电压为设计目标而引起的锁相速度慢的问题,对其进行改进,采用了前置相序分解以滤除负序分量,同时为了避免频率变动对前置相序分解的影响,将锁相频率输出经处理后送回前置相序分解,以提高锁相精度。首先分析了dq锁相环模型,推导了其稳定条件与环路带宽的设计原则;然后对一种延时相序分解法进行分析,并推导其谐波与频率特性,验证了其用于dq锁相环的有效性;最后,基于电磁暂态仿真软件PSCAD/EMTDC的仿真结论验证了前置相序分解型dq锁相环的有效性。For traditional dq-PLL,negative sequence voltage should be suppressed in unbalanced input voltage conditions to gain accurate phase output,thus it will lead to lower response character.A novel anti-SSM（Sequence Separation Method） based dq-PLL with frequency adaptive character is proposed to gain better performance.Firstly,the model of dq-PLL is analyzed in this paper,and on this base,the steady boundary of control parameters and the design principles are deduced.Secondly,one SSM based on simple signal delay is introduced,and its harmonic and frequency characters are also deduced.Lastly,simulated model of anti-SSM dq-PLL was set up by PSCAD/EMTDC software,and the validities of proposed PLL are verified by simulated results.

关 键 词：dq锁相环 前置相序分解 不平衡 性能分析 

分 类 号：TN911.9[电子电信—通信与信息系统] TM743[电子电信—信息与通信工程]