基于DDLMS算法的信道均衡器的FPGA实现  

FPGA Implementation of a Channel Equalizer Based on DDLMS Algorithm

作　　者：白勇博[1] 陈自力[1] 祁栋升[1] 

机构地区：[1]军械工程学院,河北石家庄050003

出　　处：《无线电工程》2011年第2期10-12,共3页Radio Engineering

摘　　要：无线通信系统中均衡技术是改善信道特性解决码间干扰的有效方法。从分析判决引导最小均方误差算法(DDLMS)算法出发,研究了其在信道均衡技术上的应用,并通过Matlab仿真和软件(Xilinx System Generator for DSP)开发软件在FPGA上实现了一个基于DDLMS算法的基带均衡器。从仿真测试结果可以看出,实现的信道均衡器能够达到消除码间干扰的效果。Channel equalization is an essential technology for wireless communication to improve channel performance and reduce the ISI. Based on the analysis on the DDLMS algorithm, the application of this algorithm in channel equalizer is studied. MATLAB is used to simulate the algorithm. A Channel Equalizer based on DDLMS algorithm is implemented with a development software Xilinx System Generator for DSP. The simulation test results show the equalizer can eliminate ISI.

关 键 词：DECISION Directed LMS算法 信道均衡器 FPGA 

分 类 号：TN911.5[电子电信—通信与信息系统]