应用于频率合成器的宽分频比CMOS可编程分频器设计  

Design of Programmable Wide-band Frequency Divider for Frequency Synthesizer

作　　者：鞠英[1] 文光俊[1] 杨拥军[1] 

机构地区：[1]电子科技大学通信与信息工程学院射频集成电路与系统研究中心,四川成都611731

出　　处：《现代电子技术》2011年第4期162-165,共4页Modern Electronics Technique

基　　金：省部产学研结合项目(2009A90100019)

摘　　要：提出一种应用于射频频率合成器的宽分频比可编程分频器设计。该分频器采用脉冲吞吐结构,可编程计数器和吞脉冲计数器都采用改进的CMOS源极耦合（SCL）逻辑结构的模拟电路实现,相对于采用数字电路实现降低了电路的噪声和减少了版图面积。同时,对可编程分频器中的检测和置数逻辑做了改进,提高分频器的工作频率及稳定性。最后,采用TSMC的0.13μm CMOS工艺,利用Cadence Spectre工具进行仿真,在4.5 GHz频率下,该分频器可实现200515的分频比,整个功耗不超过19 mW,版图面积为106μm×187μm。The design of a programmable frequency divider, which has wide frequency dividing ratio and is applied to RF frequency synthesizer, is presented. A pulse swallow architecture and a new detecting and reloading algorithm is adopted to improve the divider＇s speed. Programmable counter and pulse swallow counters are used to optimize the CMOS source-coupled （SCL） logical structure of the analog circuit. The process of TSMC＇s 0. 13 tim CMOS and the tool of Cadence Spectre are employed in the design to implement the simulation. The divider can implement the division ratio of 200-515 at the maximum operating frequency of 4.5 GHz. Its power consumption is less than 19 mW and domain territory is 106 μm× 187 μm.

关 键 词：可编程分频器 吞脉冲结构 4/5预分频器 检测和置数逻辑 

分 类 号：TN73-34[电子电信—电路与系统]