(2,1,7)卷积码编译码器的FPGA实现  

Implementation of (2,1,7) Convolutional Coder/Decoder in FPGA

作　　者：郭勇[1] 杨欢[1] 

机构地区：[1]南京北方信息产业集团有限公司产品研发中心,江苏南京211153

出　　处：《通信技术》2011年第1期22-23,26,共3页Communications Technology

摘　　要：卷积码是一种重要的前向纠错信道编码方式,其纠错性能常常优于分组码,且(2,1,7)卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog HDL语言设计出(2,1,7)卷积码的编码器模块和基于Viterbi算法的译码器模块,译码器采用全并行结构,译码速度快。阐述了编译码器各模块的设计原理,并在ModelSim给出各模块的仿真测试结果。同时对译码器进行纠错性能测试,测试结果表明该Viterbi译码器有良好的纠错性能。Convolutional coding is an important type of FEC channel coding,and its error-correction ability is usually superior to the group coding.（2,1,7） convolutional coding is implemented in modern satellite communications systems.Viterbi algorithm could achieve the best decoding performance of convolutional coding.This paper describes the design of（2,1,7） convolutional coding module and decoding module with verilog HDL.The decoder is all-parallel architecture,and fairly high in decoding speed.The paper also explains the principle for designing various modules of the coder/decoder,and in Modelsim,gives the simulation test result of various modules.The error-correction test of the decoder is done,and the test result indicates that the viterbi decoder has fairly good error-correction ability.

关 键 词：VITERBI ACS MODELSIM BMU FPGA 

分 类 号：TN911.22[电子电信—通信与信息系统]