A low-power 10-bit 250-KSPS cyclic ADC with offset and mismatch correction  

作　　者：赵宏亮 赵毅强 耿俊峰 李鹏 张之圣 

机构地区：[1]School of Electronic Information Engineering,Tianjin University [2]China College of Physics,Liaoning University

出　　处：《Journal of Semiconductors》2011年第2期114-119,共6页半导体学报（英文版）

基　　金：Project supposed by the Science and Technology Program of Tianjin,China(No.08ZCKFGX00200)

摘　　要：A low power 10-bit 250-k sample per second （KSPS） cyclic analog to digital converter （ADC） is presented. The ADC＇s offset errors are successfully cancelled out through the proper choice of a capacitor switching sequence. The improved redundant signed digit algorithm used in the ADC can tolerate high levels of the comparator＇s offset errors and switched capacitor mismatch errors. With this structure, it has the advantages of simple circuit configuration, small chip area and low power dissipation. The cyclic ADC manufactured with the Chartered 0.35 μm 2P4M process shows a 58.5 dB signal to noise and distortion ratio and a 9.4 bit effective number of bits at a 250 KSPS sample rate. It dissipates 0.72 mW with a 3.3 V power supply and occupies dimensions of 0.42 × 0.68 mm2.A low power 10-bit 250-k sample per second （KSPS） cyclic analog to digital converter （ADC） is presented. The ADC＇s offset errors are successfully cancelled out through the proper choice of a capacitor switching sequence. The improved redundant signed digit algorithm used in the ADC can tolerate high levels of the comparator＇s offset errors and switched capacitor mismatch errors. With this structure, it has the advantages of simple circuit configuration, small chip area and low power dissipation. The cyclic ADC manufactured with the Chartered 0.35 μm 2P4M process shows a 58.5 dB signal to noise and distortion ratio and a 9.4 bit effective number of bits at a 250 KSPS sample rate. It dissipates 0.72 mW with a 3.3 V power supply and occupies dimensions of 0.42 × 0.68 mm2.

关 键 词：cyclic ADC improved RSD algorithm low power offset cancelling 

分 类 号：TN792[电子电信—电路与系统]