一种低功耗结构的ADC设计  

Design of A novel low-power structure ADC

作　　者：高静[1] 姚素英[1] 徐江涛[1] 

机构地区：[1]天津大学电子信息工程学院,天津300072

出　　处：《电路与系统学报》2011年第1期104-107,共4页Journal of Circuits and Systems

基　　金：国家自然科学青年基金项目(60806010);国家自然科学基金项目(60976030);天津市科技支撑计划重点项目(09ZCGYGX01100)

摘　　要：逐次逼近结构ADC是中速中高分辨率应用中的常见结构,其中DAC多采用电容阵列结构,但其动态功耗随分辨率的增加而增加。论文设计了一种新颖的10位ADC结构,它采用两级进行模数转换的方法,高位采用低功耗的并行模数转换结构,低位采用逐次逼近模数转换结构,通过合理设计高低位转换位数、低功耗比较器,采用简单的二进制搜索算法,有效减小了电路动态功耗和电容阵列面积。该ADC电容阵列面积约为普通逐次逼近ADC面积的1/8,动态功耗相应降低,电路速度提高了近30%。Successive：approximation analog-to-digital converter （SAR ADC） is the most common structure in middle-speed and middle or high-resolution application. The DAC in the ADC usually adopts capacitor-array structure and the dynamic power consumption increases with the improvement of the resolution. A novel structure of 10-bit ADC is proposed in the paper which adopts two-stage converter structure. Parallel architecture is used in coarse converter, while successive-approximation architecture is used in fine converter. Combining with reasonable design of coarse and fine converter bits, low-power comparator and simple binary search algorithm, the area of the capacitor array of the ADC is just 1/8 of the traditional SAR ADC, and converter speed increases near 30%.

关 键 词：比较器 电容阵列 动态功耗 

分 类 号：TN402[电子电信—微电子学与固体电子学]