基于FPGA的三模冗余容错技术研究  

Research of TMR-Based Fault-Tolerance Techniques Based on FPGA

作　　者：张超[1] 赵伟[1] 刘峥[1] 

机构地区：[1]西安电子科技大学雷达信号处理国家重点实验室,陕西西安710071

出　　处：《现代电子技术》2011年第5期167-171,共5页Modern Electronics Technique

基　　金：陕西省自然科学基础研究计划项目(SJ08F19)

摘　　要：基于SRAM的FPGA对于空间粒子辐射非常敏感,很容易产生软故障,所以对基于FPGA的电子系统采取容错措施以防止此类故障的出现是非常重要的。三模冗余(TMR)方法以其实现的简单性和效果的可靠性而被广泛用于对单粒子翻转(SEU)进行容错处理。但传统TMR方法存在系统硬件资源消耗较多且功耗较大等问题。总结了传统TMR方法存在的问题,分析了一些近年来出现的改进的TMR方法的优劣,针对其存在问题指出了改进策略,并展望了TMR技术的发展趋势。SRAM-based FPGA are especially susceptible to radiation generated by spacial particles and are easily to get soft error,so it is quite important to adopt a measure of fault-tolerance to mitigate this kind of error in electronic systems based on FPGA.The triple modular redundancy（TMR） is a widely-used fault-tolerance technique for protecting FPGA against single-event upset（SEU）,because of its straightforward implementation and reliable result.Unfortunately,the traditional TMR method has high expense in terms of system hardware resources and power consumption.The defects of traditional TMR method are summarized.The merits and disadvantages of several new strategies to ameliorate TMR in recent years are analyzed.The solutions to solve the existed problems are offered.The development tendency of TMR technology is pointed out.

关 键 词：TMR 容错 FPGA SEU 重构 

分 类 号：TN4-34[电子电信—微电子学与固体电子学]