基于FPGA高速并行采样技术的研究  

Research of High-speed Parallel Sampling Technology Based on FPGA

作　　者：洪萌[1] 耿相铭[1] 

机构地区：[1]上海交通大学电子工程系,上海200240

出　　处：《现代电子技术》2011年第5期180-182,共3页Modern Electronics Technique

摘　　要：介绍一种基于四通道ADC的高速交错采样设计方法以及在FPGA平台上的实现。着重阐述四通道高速采样时钟的设计与实现、高速数据的同步接收以及采样数据的校正算法。实验及仿真结果表明,同步数据采集的结构设计和预处理算法,能良好抑制并行ADC输出信号因相位偏移、时钟抖动等造成的失配误差。The design method of a high-speed interleaved sampling system based on four-channel analog-to-digital converter（ADC） and its realization on Virtex-5 FPGA platform of Xilinx are introduced.The design of four-channel high-speed sampling clock,the synchronus receiving method of high-speed data and correction algorithm of sampling data are emphasized.Simulation results indicate that the structural design of the synchronus data sampling system and the pre-processing algorithm can suppress the mismatch error of parallel ADC output signal,which is caused by phase deviation and clock jittering.

关 键 词：交错采样 高速采样时钟 同步接收 信号处理 

分 类 号：TN911-34[电子电信—通信与信息系统]