Design for Testability Features of Godson-3 Multicore Microprocessor  

作　　者：齐子初 刘慧 李向库 胡伟武 

机构地区：[1]Key Laboratory of Computer System and Architecture,Chinese Academy of Sciences [2]Institute of Computing Technology,Chinese Academy of Sciences [3]Loongson Technologies Corporation Limited

出　　处：《Journal of Computer Science & Technology》2011年第2期302-313,共12页计算机科学技术学报（英文版）

基　　金：Supported by the National High-Tech Research and Development 863 Program of China under Grant Nos. 2008AA010901,2009AA01Z125,2009AA01Z103;the National Natural Science Foundation of China under Grant Nos. 60736012,60921002,60803029,61050002;the National Basic Research 973 Program of China under Grant No. 2005CB321600;the Important National Science and Technology Specific Projects under Grant Nos. 2009ZX01028-002-003,2009ZX01029-001-003

摘　　要：This paper describes the design for testability （DFT） challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar （SMOC） on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources. To achieve a scalable and flexible test access, a highly elaborate test access mechanism （TAM） is implemented to support multiple test instructions and test modes. Taking advantage of multiple identical cores embedding in the processor, scan partition and on-chip comparisons are employed to reduce test power and test time. Test compression technique is also utilized to decrease test time. To further reduce test power, clock controlling logics are designed with ability to turn off clocks of non-testing partitions. In addition, scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes, which poses low complexity and has good correlation results.This paper describes the design for testability （DFT） challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar （SMOC） on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources. To achieve a scalable and flexible test access, a highly elaborate test access mechanism （TAM） is implemented to support multiple test instructions and test modes. Taking advantage of multiple identical cores embedding in the processor, scan partition and on-chip comparisons are employed to reduce test power and test time. Test compression technique is also utilized to decrease test time. To further reduce test power, clock controlling logics are designed with ability to turn off clocks of non-testing partitions. In addition, scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes, which poses low complexity and has good correlation results.

关 键 词：DFT （design for testability） TAM （test access mechanism） multicore processor low power test 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]