DVB-C系统中RS译码器的设计  

Design of RS Decoder Based on DVB-C

作　　者：高松[1] 彭大芹[1] 刘华平 

机构地区：[1]重庆邮电大学,重庆400065 [2]重庆四联微电子有限公司,重庆401121

出　　处：《电视技术》2011年第5期10-12,44,共4页Video Engineering

基　　金：重庆市重大科技攻关项目(CSTC;2009AA2027)

摘　　要：在对DVB-C系统信道外码的Matlab仿真的基础上,介绍了RS译码器各部分的实现结构,设计了一种用于DVB-C系统的RS译码器。基于改进的Euclidean算法,并用三级流水线结构实现以提高吞吐率,在FPGA中验证了设计的可行性与可靠性。A RS decoder for the DVB-C system based on the Matlab simulation of the channel outer coder of DVB-C system is designed.The implementation structure of RS decoder is introduced. Based on the modified Euclidean algorithm, the design is implemented with three pipelined to increase throughput, its feasibility and reliability are verified in the FPGA.

关 键 词：DVB—C RS译码器 Euclidean算法 FPGA 

分 类 号：TN941.4[电子电信—信号与信息处理]