DC-DC转换器中低压迟滞比较器的电路设计  

Circuit design of a hysteresis comparator with band-gap structure

作　　者：徐静萍[1] 

机构地区：[1]西安邮电学院电子工程学院,陕西西安710121

出　　处：《西安邮电学院学报》2011年第1期91-93,97,共4页Journal of Xi'an Institute of Posts and Telecommunications

摘　　要：传统带隙电压基准和迟滞比较器需要至少2V以上的输入电压,而且占芯片面积较大。针对低压微功耗的要求,设计一种具有带隙结构的迟滞比较器电路,工作电压可低至1.2V。整个芯片的静态电流只有40uA。电路基于Bipolar工艺设计,利用Hspice软件仿真,结果表明:根据产品的电池电压不同,设计效率高达85%,迟滞比较器的迟滞电压为8mV,翻转门限电压随输入电压和温度的变化均很小。Considering that the traditional band-gap hysteresis comparator＇s input voltage can not be lower than 2V,and the chip＇s area is very large,to meet the demands of low voltage and micro power,a hysteresis comparator with band-gap structure circuit is designed,whose chip static electric can be low to 40uA only.The circuit is completed with Hspice software based on Biploar process.Simulation results show that,the efficiency is up to 85% by different supply powers,the hysteresis voltage is 8mV,and the voltage over the limit is small when the input voltage or the temperature changes.

关 键 词：DC-DC转换器 带隙基准 迟滞比较器 BIPOLAR 

分 类 号：TN402[电子电信—微电子学与固体电子学]