A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator  

作　　者：杨思宇 张辉 付文汇 易婷 洪志良 

机构地区：[1]State Key Laboratory of ASIC and System,Fudan University

出　　处：《Journal of Semiconductors》2011年第3期88-93,共6页半导体学报（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(No.60876021);the State Key Laboratory Project,China (No.MS20080203)

摘　　要：A low power 12-bit 200-kS/s SAR ADC is proposed.This features a differential time domain comparator whose offset is cancelled by using a charge pump and a phase frequency detector instead of the preamplifiers usually needed in a high resolution comparator.The proposed ADC is manufactured in 0.18-μm CMOS technology and the measured SNR and SNDR are 62.5 dB and 59.3 dB,respectively,with a power consumption of 72μW at a 200-kS/s sampling rate.The device operates with a 1.8-V power supply and achieves a FOM of 477 fJ/conversion-step.A low power 12-bit 200-kS/s SAR ADC is proposed.This features a differential time domain comparator whose offset is cancelled by using a charge pump and a phase frequency detector instead of the preamplifiers usually needed in a high resolution comparator.The proposed ADC is manufactured in 0.18-μm CMOS technology and the measured SNR and SNDR are 62.5 dB and 59.3 dB,respectively,with a power consumption of 72μW at a 200-kS/s sampling rate.The device operates with a 1.8-V power supply and achieves a FOM of 477 fJ/conversion-step.

关 键 词：successive approximation register A/D differential time domain comparator 

分 类 号：TN792[电子电信—电路与系统] TN958