Multi-core optimization for conjugate gradient benchmark on heterogeneous processors  

作　　者：邓林 窦勇 

机构地区：[1]National Laboratory for Parallel and Distributed Processing,National University of Defense Technology

出　　处：《Journal of Central South University》2011年第2期490-498,共9页中南大学学报（英文版）

基　　金：Project(2008AA01A201) supported the National High-tech Research and Development Program of China;Projects(60833004, 60633050) supported by the National Natural Science Foundation of China

摘　　要：Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at this problem,a parallelization approach was proposed with six memory optimization schemes for CG,four schemes of them aiming at all kinds of sparse matrix-vector multiplication (SPMV) operation. Conducted on IBM QS20,the parallelization approach can reach up to 21 and 133 times speedups with size A and B,respectively,compared with single power processor element. Finally,the conclusion is drawn that the peak bandwidth of memory access on Cell BE can be obtained in SPMV,simple computation is more efficient on heterogeneous processors and loop-unrolling can hide local storage access latency while executing scalar operation on SIMD cores.Developing parallel applications on heterogeneous processors is facing the challenges of ＇memory wall＇, due to limited capacity of local storage, limited bandwidth and long latency for memory access. Aiming at this problem, a parallelization approach was proposed with six memory optimization schemes for CG, four schemes of them aiming at all kinds of sparse matrix-vector multiplication （SPMV） operation. Conducted on IBM QS20, the parallelization approach can reach up to 21 and 133 times speedups with size A and B, respectively, compared with single power processor element. Finally, the conclusion is drawn that the peak bandwidth of memory access on Cell BE can be obtained in SPMV, simple computation is more efficient on heterogeneous processors and loop-unrolling can hide local storage access latency while executing scalar operation on SIMD cores.

关 键 词：multi-core processor NAS parallelization CG memory optimization 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]