Emcient Architecture for 2-Dimensional Discrete Wavelet Transform with Novel Lifting Algorithm  

作　　者：WANG Chao CAO Peng 

机构地区：[1]National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China

出　　处：《Chinese Journal of Electronics》2010年第1期1-6,共6页电子学报（英文版）

摘　　要：In commonly-used line-based implementa- tion for Two-dimensional Discrete wavelet transform （2DDWT）, data buffer is required between the row DWT processor and the column DWT processor to reorder the data flow into consistent sequence, which increases the onchip memory size, output latency and control complexity. Based on the proposed Decomposed lifting algorithm （DLA）, image data is processed in raster scan manner both in row processor and column processor. Theoretical analysis indicates that the precision of DLA outperforms other lifting-based algorithms in terms of round-off noise and internal word-length. An efficient line-based architecture is designed to perform 2D DWT based on DLA with high performance and low memory by eliminating the implementation of data buffer. For an N ×N image, only 4N internal memory is required for 9/7 filter with output latency of 2N clock cycles. Compared with related 2D DWT architectures, the size of on-chip memory and output latency are reduced significantly under the same arithmetic cost memory bandwidth and timing constraint. This design was implemented in SMIC 0.18μm CMOS logic fabrication with 32K bits dual-port RAM and 20K equivalent 2-input NAND gates in a 1.2mm×l.lmm die, which can perform 5-level Mallat decomposition at 36.17frames/s with image resolution up to 1920×1080 pixels in YUV422 full color format under 100MHz.

关 键 词：Discrete wavelet transform （DWT） LIFTING Line-based. 

分 类 号：TP311.131[自动化与计算机技术—计算机软件与理论] TN919.81[自动化与计算机技术—计算机科学与技术]