Research of Efficient Utilization Routing Algorithm for Current FPGA  

作　　者：XIE Dind LAI Jinmei TONG Jiarong 

机构地区：[1]ASIC and System State Key Laboratory, Fudan University, Shanghai 201203, China

出　　处：《Chinese Journal of Electronics》2010年第1期48-52,共5页电子学报（英文版）

摘　　要：Current FPGAs contain routing resources of diiTerent lengths and connectivity, and the connection relation of which are described by hierarchical General routing matrix （GRM）. In this paper, we present a practical routing algorithm which can represent the complex driving relationships contained in GRMs and utilize routing resources more efficient for GRM based FPGAs. First, we build Routing resource graph （RRG） by a bottom-up way, then employ A＊ directed search algorithm while dynamically updating the base cost of routing resource nodes, so that the utilization rate of routing resources can be enhanced, and this routing algorithm has high-adaptabillty to latest FPGA architectures. The experiment result shows that the utilization rate of hex lines and long lines has been raised by 6%and 8% respectively.

关 键 词：Field-programmable gate arrays（FPGA） General routing matrix （GRM） Routing re-source graph （RING） Utilization rate of routing resources 

分 类 号：TP393[自动化与计算机技术—计算机应用技术] TN791[自动化与计算机技术—计算机科学与技术]