SIMULATION AND PERFORMANCE ANALYSIS OF NETWORK ON CHIP ARCHITECTURES  

片上网络体系结构仿真和性能分析(英文)

作　　者：葛芬[1] 吴宁[1] 

机构地区：[1]南京航空航天大学信息科学与技术学院

出　　处：《Transactions of Nanjing University of Aeronautics and Astronautics》2010年第4期326-332,共7页南京航空航天大学学报（英文版）

基　　金：Supported by the Natural Science Foundation of China(61076019);the China Postdoctoral Science Foundation(20100481134);the Natural Science Foundation of Jiangsu Province(BK2008387);the Graduate Student Innovation Foundation of Jiangsu Province(CX07B-105z)~~

摘　　要：The network on chip（NoC）is used as a solution for the communication problems in a complex system on chip（SoC）design.To further enhance performances,the NoC architectures,a high level modeling and an evaluation method based on OPNET are proposed to analyze their performances on different injection rates and traffic patterns.Simulation results for general NoC in terms of the average latency and the throughput are analyzed and used as a guideline to make appropriate choices for a given application.Finally,a MPEG4 decoder is mapped on different NoC architectures.Results prove the effectiveness of the evaluation method.片上网络(Network on chip,NoC)是复杂片上系统(System on chip,SoC)设计中通信问题的解决方案。本文介绍了多种NoC体系结构,并提出了一种基于OPNET的高层次建模和仿真方法,以根据平均延时和吞吐量评估体系结构性能。本文在不同通信负载和通信模式下对NoC体系结构进行了仿真实验,对比分析的实验结果可为特定应用的NoC设计中选择最佳互连体系结构提供依据。最后通过MPEG4解码器映射到各种NoC体系结构的应用,进一步证明了该仿真评估方法的有效性。

关 键 词：microprocessor chips ARCHITECTURE network on chip system on chip performance analysis 

分 类 号：TN47[电子电信—微电子学与固体电子学]