部分响应CPM信号解调器的FPGA设计  

Design of Partial Responses CPM Demodulator based on FPGA

作　　者：李燕斌[1] 骆小谚[2] 李寅博[1] 

机构地区：[1]中国电子科技集团公司第十研究所通信事业部,四川成都610000 [2]电子科技大学电子工程学院,四川成都610054

出　　处：《通信技术》2011年第2期13-15,共3页Communications Technology

摘　　要：设计并实现了一种基于FPGA的二进制连续相位调制(CMP)解调器。该解调器针对二进制部分响应调制方式,采用Viterbi译码方法进行解码。文中针对路径度量值随着译码序列增长可能发生溢出的现象,提出了一种新的防止路径度量值溢出方法。最后使用VHDL硬件描述语言将该解调器的设计进行实现,运用Modelsim仿真软件进行了功能仿真,并将仿真结果与MATLAB数据比较分析。该解调器的FPGA设计能够得到正确的解码结果,最终证明了该方法的有效性。A binary partial responses continual phase modulation（CMP） based on FPGA is designed and implemented.This demodulator is suitable for the binary partial response modulation system based on the Viterbi algorithm.A new method is proposed to avoid path value overflow with decoded sequence growth.A demodulator is designed and implemented by using the VHDL hardware description language,and function simulation is done by Modelsim.In this paper,the comparison of function simulation result with MATLAB data is given.This FPGA-based demodulator could achieve correct decoding result,and the simulation indicates that this demodulator is feasible and effective,and the design is quite correct and applicable.

关 键 词：连续相位调制 现场可编程门阵列 Viterb译码 

分 类 号：TN764[电子电信—电路与系统]