高吞吐率XTS-AES加密算法的硬件实现  

A High-Throughput Hardware Implementation of XTS-AES Encryption Algorithm

作　　者：李子磊[1] 刘政林[1] 霍文捷[1] 邹雪城[1] 

机构地区：[1]华中科技大学电子科学与技术系,湖北武汉430074

出　　处：《微电子学与计算机》2011年第4期95-98,102,共5页Microelectronics & Computer

基　　金：国家自然科学基金项目(60973034);2007新世纪优秀人才支持计划项目(NCET-07-0328)

摘　　要：基于XTS-AES算法提出了一种具有并行全流水结构的硬件实现方法.设计通过展开数据通路的方式,提高了吞吐率;同时还通过采用内部流水线结构优化关键路径的方式,提高了电路的时钟频率和整体工作性能.在UMC 90 nm CMOS工艺条件下,所设计的XTS-AES模块的吞吐率比目前已知XTS-AES的最高吞吐率提高了52.28%.分析结果表明,该硬件模块完全满足现阶段高速加密存储的需要.This paper proposes a new hardware implementation method for XTS-AES Algorithm that has a full paral- lel pipelined structure. The proposal scheme increases throughput by unrolling the data path. Meanwhile, it also im- proves the circuit clock frequency and overall performance by using inner pipelined structure to optimize the critical path. Compared with the currently known highest throughput XTS-AES implementation,the new XTS^AES module increases the throughput by 52.28% in UMC 90 nm CMOS technology. The result indicates that this hardware mod ule fully meets the need of high speed encrypted storage at present.

关 键 词：高速存储 高吞吐率 并行全流水结构 XTS-AES加密算法 

分 类 号：TN4[电子电信—微电子学与固体电子学]