CMMB系统中的LDPC码性能分析及译码器VLSI实现(英文)  

Performance Analysis and VLSI Implementationof LDPC Decoder for CMMB System

作　　者：刘海洋[1] 张浩[1] 曲文泽[1] 陈杰[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《系统仿真学报》2011年第4期798-802,共5页Journal of System Simulation

基　　金：supported by the Major State Basic Research Development Program of China(2009CB320304)

摘　　要：对CMMB标准中的LDPC码进行了研究。分析了该标准中两种不同码率的LDPC码采用和-积算法和最小-和算法的浮点性能,得出在相同迭代次数的条件下最小-和算法的性能接近和-积算法。选择最小-和算法进行VLSI实现,并提出了一种有效的量化方案。仿真结果表明,量化后的性能相对于浮点运算的性能几乎没有性能损失。此外,设计了LDPC译码器的VLSI结构并且在Altera Stratix II EP2S130器件上进行了综合验证。综合结果表明,设计的译码器的最大时钟频率为90.7 MHz,在该频率下可以达到49.1 Mbps的高吞吐率,完全满足CMMB标准要求。The LDPC codes used in the CMMB standard were studied.The floating point performance of the LDPC codes of two different rates in the standard was analyzed for the sum-product algorithm and min-sum algorithm.At the same number of iterations,the performance of the min-sum algorithm was closed to that of the sum-product algorithm.The min-sum algorithm was chosen for VLSI implementation and an efficient quantization scheme was proposed.Simulation results show that the quantized version has nearly no performance degradation compared with the floating point version.Moreover,the VLSI architecture for the LDPC decoder was designed and implemented in an Altera Stratix II EP2S130 device.The synthesis results show that the designed decoder is able to operate at the maximum clock frequency of 90.7 MHz.At this frequency,the decoder can achieve the throughput up to 49.1 Mbps,which is sufficient for the CMMB standard.

关 键 词：LDPC码 CMMB 和-积算法 最小-和算法 量化方案 VLSI实现 

分 类 号：TP391.9[自动化与计算机技术—计算机应用技术]