基于Avalon总线的m序列码组件设计  

Module Design of M-sequence Code Based on Avalon Bus

作　　者：郑恭明[1] 

机构地区：[1]长江大学电子信息学院,湖北荆州434023

出　　处：《成都大学学报（自然科学版）》2011年第1期78-81,共4页Journal of Chengdu University（Natural Science Edition）

摘　　要：在Nios Ⅱ系统中,按照Avalon总线规范将各种自定义外设的驱动程序集成到SOPC的硬件抽象层中进行设计复用,以提高设计效率,缩短后继开发周期.伪随机m序列因具有良好的随机性和接近于白噪声的相关函数,在多个领域得到广泛的应用.根据Avalon总线规范,采用软硬件协同设计的方法,实现了阶次与码字时长可调的m序列码组件设计.The design efficiency can be improved and the development cycle can be shortened by the means of integrating various user-defined peripheral driver set to hardware abstract layer of SOPC system according to the norm of Avalon bus in Nios II system.Pseudo-random sequence with good randomness and correlation function closing to white noise is widely used in many fields.According to the Avalon bus specification,hardware and software co-design method was used to achieve m-sequence design in which order and code length is adjustable.

关 键 词：M序列 AVALON总线 组件设计 SOPC BUILDER 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]