一种基于CPLD高速大容量双端口RAM电路系统的设计  

A Design of Circuit System Based on CPLD in Dual-Port RAM

作　　者：葛学峰[1,2] 时斌[1] 朱晓舒[1] 罗小兵[3] 

机构地区：[1]南京师范大学分析测试中心,江苏南京210046 [2]南京航空航天大学理学院,江苏南京211106 [3]南京师范大学物理科学与技术学院,江苏南京210046

出　　处：《南京师范大学学报（工程技术版）》2011年第1期68-72,共5页Journal of Nanjing Normal University(Engineering and Technology Edition)

基　　金：国家自然科学基金(07KJA51001)

摘　　要：双端口RAM在智能仪器高速数据采集中扮演着重要的作用.提出了一种高速、大容量、低成本的双端口随机存储器(RAM)的设计方案,该方案通过对复杂可编程(CPLD)进行逻辑电路设计实现.仿真结果表明,双端口RAM的读写控制时序完全符合双端口RAM的时序要求,读写结果正确.解决了目前市场上缺少高速、大容量、低成本的双端口RAM的问题,方便高速数据采集与处理仪器的快速开发.Dual-port RAM plays an important role in intelligent instrument of high-speed data acquisition. The scheme and the circuit of dual-port RAM, which are high in speed, large in volume and low in cost, are introduced in this paper. The approach was adopted by programming logic circuit in complicated programmable logic device （CPLD）. The simulation result of dual-port RAM is verified correct in the timing, the outcome of reading operation and writing operation. The design, which helps the quick development of data sampling and processing instrument, solves the shortage of high-speed, large-volume and low-cost dual-port RAM.

关 键 词：CPLD 双端口RAM 数据采集 

分 类 号：TH865[机械工程—仪器科学与技术]