基于FPGA的双边沿移位寄存器设计  

Design of Double Edge Shift Register Based on FPGA

作　　者：曾菊容[1] 

机构地区：[1]宜宾学院物理与电子工程系,四川宜宾644000

出　　处：《陇东学院学报》2011年第2期35-37,共3页Journal of Longdong University

摘　　要：针对单边沿触发器功耗大的缺点,提出了一种双边沿触发的移位寄存器设计方法。利用双边沿检测技术在输入时钟的两个边沿分别输出一个窄脉冲,利用该窄脉冲控制移位寄存器,这样时钟频率相对于单边沿触发时减少了一半,功耗明显降低。改变移位寄存器模块的参数,可以实现任意长度的移位寄存器。采用VHDL和原理图输入方式,在QuartusΠ平台下实现本设计的综合和仿真,并用ACEX1K30芯片实现,实验证明了设计的有效性和可靠性。This paper describes a design method of shift register which triggers by double edge aiming at the big power dissipation of single trigger.Use double edge detection technique to detect the two edges of the clock signal and output a narrow pulse respectively at these edges.Then use these narrow pulses to control shift register.Thus the power dissipation can be reduced evidently because of using the clock with half working frequency,in comparison with single edge trigger.It can realize shift register which length is arbitrarily when we changes the parameter of shift register.This design implemented with an ACEX1K30 chip described in VHDL,and synthesized and simulated with Quartus Π.The results in the experiment confirmed the validity and reliability of the design.

关 键 词：FPGA 双边沿检测 移位寄存器 窄脉冲 低功耗 

分 类 号：TN791[电子电信—电路与系统]